1. Field of the Invention
The present invention relates to an interrupt control circuit, and more particularly to interrupt control circuit and method for providing information necessary for handling plural interrupt requests with a processor.
2. Description of Related Art
In recent years, application-specific embedded systems have been widely used in the fields of household electrical appliance and automobile and various other fields. In the embedded systems, a processor should control more and more units, which leads to an increase in the number of interrupt signals to be processed with the processor. For example, if the processor needs to control an electronic control unit, data backup as well as system control should be carried out in some cases. In such cases, the processor receives an interrupt request for the system control and an interrupt request for the data backup.
Interrupt handling for the system control cannot keep pace with state changes of the electronic control unit unless being completed during a predetermined period. As a result, a failure would occur upon the system control. Hence, a real-time response is required of the processor to surely complete interrupt handling for the system control during a predetermined period from when an interrupt occurred and send back the processing result. On the other hand, as for interrupt handling for the data backup, no particular problem occurs even if a period from the interrupt occurrence to the completion of handling varies from time to time. Hence, the processor does not need to have so high response.
An allowable processing time of the processor varies depending on operational conditions of the electronic control unit. For example, if an operation speed of the electronic control unit is high, the processing time is short. If the speed is low, the time is long. If the allowable processing time of the processor is short or the number of actions to be processed increases, high throughput is required of the processor. Hence, if the processor can accept all interrupt handling requests, and an excessive number of interrupts occur, it is impossible to handle all the interrupts in some cases. To that end, the processor is provided with an interrupt control circuit for controlling interrupt handling in such a manner that an interrupt to be handled in non-real time is temporarily masked and held, and an interrupt to be handled in real time is processed if the throughput of the processor is not so high.
Japanese Unexamined Patent Application Publication No. 2005-284760 discloses a conventional interrupt control circuit example. Japanese Unexamined Patent Application Publication No. 2005-284760 describes a method of grouping plural interrupt requests and setting a mask on a group basis. According to this method, a predetermined interrupt request out of the plural interrupt requests can be easily masked.
However, the inventors of the subject application have found that the related art faces the following problems. In the related art, there is a possibility that a higher-priority interrupt request is masked while the processor excutes interrupt handling. The processor checks each register storing interrupt requests and determines whether or not any masked interrupt request remains. If the number of registers to be checked by the processor is small, no particular problem arises. However, if the processor should check as many registers as several tens to several hundreds of registers, it takes lots of time to check all the registers.